Silicon carbide wafers are widely used in power electronics, RF devices, high-temperature electronics and semiconductor research. However, two SiC wafers with the same diameter and thickness can perform very differently during epitaxy or device fabrication.
Crystal defects, surface damage, geometric variation, resistivity non-uniformity and contamination may all affect process yield and device reliability. Therefore, checking only the wafer diameter and surface appearance is not enough.
This guide explains the most important SiC wafer inspection items, how they are measured and what buyers should request from a supplier before approving a production lot.
SiC wafer quality is usually evaluated in five main areas:
The importance of each item depends on the intended application. A device-grade substrate prepared for epitaxial growth normally requires tighter controls than a research wafer, dummy wafer or equipment calibration wafer.
There is no single specification that defines a “good” SiC wafer for every application. The correct acceptance limits should be established according to the device process, wafer size, conductivity type and required production yield.
| Inspection item | Why it matters | Common inspection method |
|---|---|---|
| Polytype | Determines material and electrical characteristics | Raman spectroscopy, XRD |
| Crystal orientation | Affects epitaxy and device fabrication | X-ray diffraction |
| Off-axis angle | Influences step-flow epitaxial growth | High-resolution XRD |
| Micropipes | May cause catastrophic device failure | Optical inspection, X-ray topography, defect mapping |
| Dislocations | Can affect leakage, breakdown and reliability | PL mapping, X-ray topography, etching |
| Diameter and thickness | Determines equipment and process compatibility | Dimensional metrology |
| TTV | Affects lithography, grinding and process uniformity | Capacitive or optical measurement |
| Bow and warp | Affect chucking, focus and handling | Non-contact optical metrology |
| Surface roughness | Influences epitaxial layer quality | AFM |
| Scratches and pits | May become nucleation or failure sites | Optical and laser-scattering inspection |
| Resistivity | Determines electrical performance | Four-point probe, eddy-current or contactless testing |
| Doping uniformity | Affects device consistency across the wafer | Resistivity mapping, Hall measurement |
| Surface contamination | May reduce yield or introduce defects | Particle inspection, TXRF, XPS or other analytical methods |
| Edge quality | Influences wafer breakage and handling | Edge inspection and microscopy |
Silicon carbide has many crystal structures, known as polytypes. The most common semiconductor grades are 4H-SiC and 6H-SiC.
Today, 4H-SiC is commonly selected for power devices because of its favorable carrier mobility, wide bandgap and high critical electric field. However, 6H-SiC may still be used for certain research, optical or specialized applications.
The polytype should be clearly stated on the certificate of analysis. Raman spectroscopy and X-ray diffraction can be used to confirm the crystal structure and identify possible polytype inclusions.
A buyer should not assume that all SiC wafers have the same crystal structure simply because they have the same color, diameter or conductivity type.
Most commercial 4H-SiC substrates are produced with a defined crystallographic orientation, commonly based on the (0001) plane. The wafer may also have a specified off-axis angle and direction.
The off-axis orientation is particularly important for epitaxial growth. It supports step-flow growth and helps control the formation of undesirable crystal structures in the epitaxial layer.
Important orientation information may include:
X-ray diffraction is commonly used to verify crystal orientation and offcut. When ordering wafers for epitaxy, the buyer should specify both the nominal off-axis angle and the acceptable tolerance.
Crystal defects are among the most important factors affecting SiC wafer quality.
A micropipe is a hollow-core defect associated with a large screw dislocation. It can pass through the substrate and interfere with epitaxial growth or device fabrication.
Micropipes were once a major limitation in SiC manufacturing. Although modern crystal growth has significantly reduced their density, micropipe inspection remains important for high-voltage and high-reliability applications.
Threading screw dislocations, or TSDs, extend approximately along the crystal growth direction. They may influence breakdown behavior, leakage current and device reliability.
Their effect depends on the device structure, location and process design. Therefore, both defect density and spatial distribution may be relevant.
Threading edge dislocations, or TEDs, are commonly found in SiC substrates. Although they may be less destructive than micropipes, high densities can still affect epitaxial quality and device performance.
Basal plane dislocations, or BPDs, are important in bipolar device applications because they can contribute to the formation or expansion of stacking faults under electrical stress.
For applications sensitive to bipolar degradation, BPD density and conversion behavior during epitaxy should be carefully evaluated.
Stacking faults are interruptions in the normal stacking sequence of the SiC crystal. Polytype inclusions are regions where an unintended SiC crystal structure is present.
Both defects can interfere with epitaxy and affect electrical performance.
Common defect inspection methods include:
Some methods are non-destructive, while chemical etching is destructive. Buyers should confirm which inspection method was used and whether the reported result represents the entire wafer or only sampled areas.
Wafer diameter and thickness determine whether the substrate is compatible with processing, handling, polishing and epitaxy equipment.
Key dimensional items include:
Thickness requirements may vary according to wafer diameter and intended use. A thinner wafer may be needed for a specific device process, while a thicker substrate may offer better mechanical stability during research or equipment testing.
For custom-thickness wafers, buyers should also evaluate whether additional grinding or polishing may increase bow, warp or subsurface damage.
Total thickness variation, commonly abbreviated as TTV, is the difference between the maximum and minimum measured thickness across the wafer within a defined measurement area.
A low TTV is important because excessive thickness variation can affect:
TTV values can be influenced by the measurement method, number of measurement points and edge-exclusion area. Therefore, a specification should not state only a maximum TTV value. It should also identify the agreed measurement conditions.
Bow and warp describe the shape of a free, unclamped wafer, but they are not the same measurement.
Bow generally describes the deviation of the wafer’s median surface from a reference plane.
Warp represents the overall difference between the highest and lowest points of the median surface relative to a reference plane.
Excessive bow or warp can cause problems during:
Larger-diameter and thinner SiC wafers may be more sensitive to geometric deformation. Buyers should define the measurement method, edge exclusion and wafer support conditions when comparing data from different suppliers.
An epitaxy-ready SiC surface must be extremely smooth and free from significant polishing damage.
Atomic force microscopy, or AFM, is commonly used to measure root mean square surface roughness. However, the reported value depends strongly on the scan area, instrument settings and measurement location.
A roughness result should therefore include:
A single roughness value without a scan size or sampling plan is difficult to compare.
For wafers intended for epitaxy, surface quality should also be evaluated for polishing-related defects such as scratches, pits, residual subsurface damage and step bunching.
A wafer may look clean to the naked eye while still containing defects that affect epitaxial growth or device fabrication.
Common surface defects include:
Inspection can be performed using bright-field microscopy, dark-field microscopy, laser-scattering systems and automated surface scanners.
The acceptance criteria should define the minimum detectable defect size, allowable defect count and edge-exclusion area. Descriptions such as “mirror polished” or “scratch-free” are not sufficient unless accompanied by measurable standards.
SiC wafers have two polar surfaces: the silicon-terminated face and the carbon-terminated face. These surfaces do not behave identically during oxidation, etching, polishing or epitaxy.
The supplier should identify:
Incorrect face identification can lead to process failure, especially during epitaxial growth or surface research.
For single-side polished wafers, the buyer should also confirm whether the backside is fine-ground, etched, lapped or polished.
Electrical performance is another essential part of SiC wafer quality.
Conductive N-type SiC wafers are commonly nitrogen doped. Other doping types and semi-insulating grades are also available for specialized applications.
Important electrical parameters may include:
Four-point probe testing, contactless resistivity measurement, eddy-current mapping and Hall-effect measurement may be used depending on the wafer type and resistance range.
An average resistivity value alone may not be enough. For device manufacturing, the variation from the wafer center to the edge and from wafer to wafer within the same lot can be equally important.
For semi-insulating SiC wafers, the measurement method must be suitable for high-resistivity material. The supplier should state the test temperature, measurement range and acceptance criteria.
Metallic contamination, organic residues and particles can reduce epitaxial and device yield even when the wafer meets its geometric specifications.
Possible inspection techniques include:
Not every order requires advanced contamination testing. However, buyers should at least confirm the wafer cleaning process, final packaging environment and maximum allowable particle level when the material is intended for sensitive semiconductor fabrication.
The wafer edge affects mechanical strength and automated handling.
Inspect the edge for:
Small edge defects may grow during high-temperature processing, grinding or wafer transport. For this reason, edge inspection should be included in incoming quality control, especially for thin or large-diameter wafers.
The position and dimensions of the primary flat or notch should also match the processing equipment and crystallographic orientation requirements.
A complete certificate of analysis should clearly link the inspection results to the supplied wafer or production lot.
Depending on the order, useful documentation may include:
A lot-level average cannot always reveal local defects or wafer-to-wafer variation. For critical applications, request individual wafer data or wafer maps rather than relying only on a general batch certificate.
Traceability is also important when comparing epitaxial results, identifying process problems or evaluating long-term supplier consistency.
A bare SiC substrate and an epitaxial SiC wafer require different inspection plans.
In addition to substrate parameters, an epitaxial wafer may require evaluation of:
Buyers should clearly state whether they require a polished substrate, an epi-ready substrate or a wafer with an epitaxial layer.
A practical incoming inspection process can be divided into four steps.
Confirm that the wafer identification, purchase order, packaging label and COA refer to the same wafer or lot.
Check diameter, thickness, edge condition, surface identification and visible scratches, particles or chips.
Measure the properties most relevant to the process, such as TTV, bow, warp, roughness or resistivity.
For production use, correlate incoming inspection data with epitaxial defects, fabrication yield and final device performance. This helps determine which substrate parameters have the greatest effect on the actual process.
Before requesting a quotation, provide the following information:
Providing a complete specification reduces technical clarification time and helps the supplier select the correct wafer grade.
There is no single most important parameter for every application. Crystal defects, surface condition, geometry and resistivity must be considered together. For epitaxy, the off-axis angle, surface roughness, subsurface damage and crystal defects are often especially important.
A lower TTV generally improves process uniformity, but tighter specifications may increase manufacturing cost. The correct limit should be based on the equipment, lithography process, bonding method and final device requirements.
No. Visual inspection may identify scratches, chips, stains and large surface defects, but it cannot reveal all subsurface or crystallographic defects. PL mapping, X-ray topography, AFM and other analytical methods may be required.
Surface roughness can appear different when measured over different scan areas. An AFM result should always include the scan size, measurement location and number of sampled points.
Research-grade wafers may have wider tolerances or higher allowable defect levels. Device-grade or epi-ready wafers generally require tighter control of crystal defects, surface condition, geometry, resistivity and traceability.
A wafer-level map is recommended for applications where defect position, resistivity uniformity or local surface conditions can affect device yield. It provides more useful information than a single lot-average value.
Evaluating SiC wafer quality requires more than checking diameter, thickness and visual appearance. Crystal structure, dislocation density, TTV, bow, warp, surface roughness, resistivity, contamination and traceability can all influence epitaxial growth and device yield.
The first step is to define the wafer’s intended application. Buyers can then establish measurable acceptance criteria and request inspection results based on the parameters that directly affect their process.
When requesting a quotation, provide the polytype, diameter, orientation, conductivity, thickness, geometric tolerances, surface requirements and documentation needs. A detailed RFQ makes it easier to compare wafers accurately and avoid receiving material that meets a general description but does not match the actual application.
Silicon carbide wafers are widely used in power electronics, RF devices, high-temperature electronics and semiconductor research. However, two SiC wafers with the same diameter and thickness can perform very differently during epitaxy or device fabrication.
Crystal defects, surface damage, geometric variation, resistivity non-uniformity and contamination may all affect process yield and device reliability. Therefore, checking only the wafer diameter and surface appearance is not enough.
This guide explains the most important SiC wafer inspection items, how they are measured and what buyers should request from a supplier before approving a production lot.
SiC wafer quality is usually evaluated in five main areas:
The importance of each item depends on the intended application. A device-grade substrate prepared for epitaxial growth normally requires tighter controls than a research wafer, dummy wafer or equipment calibration wafer.
There is no single specification that defines a “good” SiC wafer for every application. The correct acceptance limits should be established according to the device process, wafer size, conductivity type and required production yield.
| Inspection item | Why it matters | Common inspection method |
|---|---|---|
| Polytype | Determines material and electrical characteristics | Raman spectroscopy, XRD |
| Crystal orientation | Affects epitaxy and device fabrication | X-ray diffraction |
| Off-axis angle | Influences step-flow epitaxial growth | High-resolution XRD |
| Micropipes | May cause catastrophic device failure | Optical inspection, X-ray topography, defect mapping |
| Dislocations | Can affect leakage, breakdown and reliability | PL mapping, X-ray topography, etching |
| Diameter and thickness | Determines equipment and process compatibility | Dimensional metrology |
| TTV | Affects lithography, grinding and process uniformity | Capacitive or optical measurement |
| Bow and warp | Affect chucking, focus and handling | Non-contact optical metrology |
| Surface roughness | Influences epitaxial layer quality | AFM |
| Scratches and pits | May become nucleation or failure sites | Optical and laser-scattering inspection |
| Resistivity | Determines electrical performance | Four-point probe, eddy-current or contactless testing |
| Doping uniformity | Affects device consistency across the wafer | Resistivity mapping, Hall measurement |
| Surface contamination | May reduce yield or introduce defects | Particle inspection, TXRF, XPS or other analytical methods |
| Edge quality | Influences wafer breakage and handling | Edge inspection and microscopy |
Silicon carbide has many crystal structures, known as polytypes. The most common semiconductor grades are 4H-SiC and 6H-SiC.
Today, 4H-SiC is commonly selected for power devices because of its favorable carrier mobility, wide bandgap and high critical electric field. However, 6H-SiC may still be used for certain research, optical or specialized applications.
The polytype should be clearly stated on the certificate of analysis. Raman spectroscopy and X-ray diffraction can be used to confirm the crystal structure and identify possible polytype inclusions.
A buyer should not assume that all SiC wafers have the same crystal structure simply because they have the same color, diameter or conductivity type.
Most commercial 4H-SiC substrates are produced with a defined crystallographic orientation, commonly based on the (0001) plane. The wafer may also have a specified off-axis angle and direction.
The off-axis orientation is particularly important for epitaxial growth. It supports step-flow growth and helps control the formation of undesirable crystal structures in the epitaxial layer.
Important orientation information may include:
X-ray diffraction is commonly used to verify crystal orientation and offcut. When ordering wafers for epitaxy, the buyer should specify both the nominal off-axis angle and the acceptable tolerance.
Crystal defects are among the most important factors affecting SiC wafer quality.
A micropipe is a hollow-core defect associated with a large screw dislocation. It can pass through the substrate and interfere with epitaxial growth or device fabrication.
Micropipes were once a major limitation in SiC manufacturing. Although modern crystal growth has significantly reduced their density, micropipe inspection remains important for high-voltage and high-reliability applications.
Threading screw dislocations, or TSDs, extend approximately along the crystal growth direction. They may influence breakdown behavior, leakage current and device reliability.
Their effect depends on the device structure, location and process design. Therefore, both defect density and spatial distribution may be relevant.
Threading edge dislocations, or TEDs, are commonly found in SiC substrates. Although they may be less destructive than micropipes, high densities can still affect epitaxial quality and device performance.
Basal plane dislocations, or BPDs, are important in bipolar device applications because they can contribute to the formation or expansion of stacking faults under electrical stress.
For applications sensitive to bipolar degradation, BPD density and conversion behavior during epitaxy should be carefully evaluated.
Stacking faults are interruptions in the normal stacking sequence of the SiC crystal. Polytype inclusions are regions where an unintended SiC crystal structure is present.
Both defects can interfere with epitaxy and affect electrical performance.
Common defect inspection methods include:
Some methods are non-destructive, while chemical etching is destructive. Buyers should confirm which inspection method was used and whether the reported result represents the entire wafer or only sampled areas.
Wafer diameter and thickness determine whether the substrate is compatible with processing, handling, polishing and epitaxy equipment.
Key dimensional items include:
Thickness requirements may vary according to wafer diameter and intended use. A thinner wafer may be needed for a specific device process, while a thicker substrate may offer better mechanical stability during research or equipment testing.
For custom-thickness wafers, buyers should also evaluate whether additional grinding or polishing may increase bow, warp or subsurface damage.
Total thickness variation, commonly abbreviated as TTV, is the difference between the maximum and minimum measured thickness across the wafer within a defined measurement area.
A low TTV is important because excessive thickness variation can affect:
TTV values can be influenced by the measurement method, number of measurement points and edge-exclusion area. Therefore, a specification should not state only a maximum TTV value. It should also identify the agreed measurement conditions.
Bow and warp describe the shape of a free, unclamped wafer, but they are not the same measurement.
Bow generally describes the deviation of the wafer’s median surface from a reference plane.
Warp represents the overall difference between the highest and lowest points of the median surface relative to a reference plane.
Excessive bow or warp can cause problems during:
Larger-diameter and thinner SiC wafers may be more sensitive to geometric deformation. Buyers should define the measurement method, edge exclusion and wafer support conditions when comparing data from different suppliers.
An epitaxy-ready SiC surface must be extremely smooth and free from significant polishing damage.
Atomic force microscopy, or AFM, is commonly used to measure root mean square surface roughness. However, the reported value depends strongly on the scan area, instrument settings and measurement location.
A roughness result should therefore include:
A single roughness value without a scan size or sampling plan is difficult to compare.
For wafers intended for epitaxy, surface quality should also be evaluated for polishing-related defects such as scratches, pits, residual subsurface damage and step bunching.
A wafer may look clean to the naked eye while still containing defects that affect epitaxial growth or device fabrication.
Common surface defects include:
Inspection can be performed using bright-field microscopy, dark-field microscopy, laser-scattering systems and automated surface scanners.
The acceptance criteria should define the minimum detectable defect size, allowable defect count and edge-exclusion area. Descriptions such as “mirror polished” or “scratch-free” are not sufficient unless accompanied by measurable standards.
SiC wafers have two polar surfaces: the silicon-terminated face and the carbon-terminated face. These surfaces do not behave identically during oxidation, etching, polishing or epitaxy.
The supplier should identify:
Incorrect face identification can lead to process failure, especially during epitaxial growth or surface research.
For single-side polished wafers, the buyer should also confirm whether the backside is fine-ground, etched, lapped or polished.
Electrical performance is another essential part of SiC wafer quality.
Conductive N-type SiC wafers are commonly nitrogen doped. Other doping types and semi-insulating grades are also available for specialized applications.
Important electrical parameters may include:
Four-point probe testing, contactless resistivity measurement, eddy-current mapping and Hall-effect measurement may be used depending on the wafer type and resistance range.
An average resistivity value alone may not be enough. For device manufacturing, the variation from the wafer center to the edge and from wafer to wafer within the same lot can be equally important.
For semi-insulating SiC wafers, the measurement method must be suitable for high-resistivity material. The supplier should state the test temperature, measurement range and acceptance criteria.
Metallic contamination, organic residues and particles can reduce epitaxial and device yield even when the wafer meets its geometric specifications.
Possible inspection techniques include:
Not every order requires advanced contamination testing. However, buyers should at least confirm the wafer cleaning process, final packaging environment and maximum allowable particle level when the material is intended for sensitive semiconductor fabrication.
The wafer edge affects mechanical strength and automated handling.
Inspect the edge for:
Small edge defects may grow during high-temperature processing, grinding or wafer transport. For this reason, edge inspection should be included in incoming quality control, especially for thin or large-diameter wafers.
The position and dimensions of the primary flat or notch should also match the processing equipment and crystallographic orientation requirements.
A complete certificate of analysis should clearly link the inspection results to the supplied wafer or production lot.
Depending on the order, useful documentation may include:
A lot-level average cannot always reveal local defects or wafer-to-wafer variation. For critical applications, request individual wafer data or wafer maps rather than relying only on a general batch certificate.
Traceability is also important when comparing epitaxial results, identifying process problems or evaluating long-term supplier consistency.
A bare SiC substrate and an epitaxial SiC wafer require different inspection plans.
In addition to substrate parameters, an epitaxial wafer may require evaluation of:
Buyers should clearly state whether they require a polished substrate, an epi-ready substrate or a wafer with an epitaxial layer.
A practical incoming inspection process can be divided into four steps.
Confirm that the wafer identification, purchase order, packaging label and COA refer to the same wafer or lot.
Check diameter, thickness, edge condition, surface identification and visible scratches, particles or chips.
Measure the properties most relevant to the process, such as TTV, bow, warp, roughness or resistivity.
For production use, correlate incoming inspection data with epitaxial defects, fabrication yield and final device performance. This helps determine which substrate parameters have the greatest effect on the actual process.
Before requesting a quotation, provide the following information:
Providing a complete specification reduces technical clarification time and helps the supplier select the correct wafer grade.
There is no single most important parameter for every application. Crystal defects, surface condition, geometry and resistivity must be considered together. For epitaxy, the off-axis angle, surface roughness, subsurface damage and crystal defects are often especially important.
A lower TTV generally improves process uniformity, but tighter specifications may increase manufacturing cost. The correct limit should be based on the equipment, lithography process, bonding method and final device requirements.
No. Visual inspection may identify scratches, chips, stains and large surface defects, but it cannot reveal all subsurface or crystallographic defects. PL mapping, X-ray topography, AFM and other analytical methods may be required.
Surface roughness can appear different when measured over different scan areas. An AFM result should always include the scan size, measurement location and number of sampled points.
Research-grade wafers may have wider tolerances or higher allowable defect levels. Device-grade or epi-ready wafers generally require tighter control of crystal defects, surface condition, geometry, resistivity and traceability.
A wafer-level map is recommended for applications where defect position, resistivity uniformity or local surface conditions can affect device yield. It provides more useful information than a single lot-average value.
Evaluating SiC wafer quality requires more than checking diameter, thickness and visual appearance. Crystal structure, dislocation density, TTV, bow, warp, surface roughness, resistivity, contamination and traceability can all influence epitaxial growth and device yield.
The first step is to define the wafer’s intended application. Buyers can then establish measurable acceptance criteria and request inspection results based on the parameters that directly affect their process.
When requesting a quotation, provide the polytype, diameter, orientation, conductivity, thickness, geometric tolerances, surface requirements and documentation needs. A detailed RFQ makes it easier to compare wafers accurately and avoid receiving material that meets a general description but does not match the actual application.
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